十月二十號的課堂練習

此為20號的課堂練習~快要期中考了,得加緊努力

2008 10/13 半加法器練習操作

module top;
wire a,b;
wire sum,c_out;

system_clock #100 clock1(a);
system_clock #50 clock2(b);

Add_half AH1(sum,c_out,a,b);

endmodule

module Add_half(sum,c_out, a, b);

input a,b;
output sum,c_out;
wire c_out_bar;


xor(sum, a, b);
nand(c_out_bar, a, b);
not(c_out,c_out_bar);
endmodule


module system_clock(clk);
parameter PERIOD = 100;
output clk;
reg clk;
initial
clk = 0;
always
begin
#(PERIOD/2) clk = ~clk;
#(PERIOD/2) clk = ~clk;
end
always@(posedge clk)
if($time > 1000) #(PERIOD-1)$stop;
endmodule

10.6日上課內容

Design a verilog model of a half adder and write a testbench to verify the designed verilog model。

module Add_half (sum,c_out,a,b);
input a,b;
output sum,c_out;
wire c_out_bar;
xor (sum,a,b);
nand (c_out_bar,a,b);
not (c_out,c_out_bar);
endmodule